Semiconductor integrated circuits are widely used at various locations. For example, various electronic apparatuses, such as an engine control apparatus, a brake control apparatus, a car navigation apparatus, and an audio apparatus are installed in vehicles.
Users of vehicles may dispose a personal radio apparatus, an amateur radio apparatus, or the like in the vehicles and use it. In this case, various electronic apparatuses in a dashboard may receive a radio wave (an electromagnetic wave) at close range.
Thus, if various electronic apparatuses installed in vehicles receive a strong electromagnetic wave at close range, they may malfunction under the influence of such a strong electromagnetic wave.
As the most effective way to avoid being influenced by an electromagnetic wave, shielding is generally performed. There are various types of shielding methods, including a method of covering the whole of an electronic apparatus and a method of partially covering the printed circuit board (PCB) of an electronic apparatus. A shielding method is determined in accordance with the balance between sensitivity to an electromagnetic wave of an electronic apparatus and a shielding cost.
An input circuit in the related art and the problem of the input circuit will be described with reference to FIGS. 1 to 3.
FIG. 1 is a circuit diagram illustrating an example of an input/output circuit (input circuit) in the related art that can be used as an input/output terminal (input terminal) in a semiconductor integrated circuit (LSI).
In this specification, for simplification of explanation, not only an original input terminal but also a terminal that can be used as both an input terminal and an output terminal are described as input terminals. Furthermore, not only an original input circuit but also a circuit functioning as both an input circuit and an output circuit are described as input circuits.
As illustrated in FIG. 1, an input circuit 100 in the related art includes a p-channel MOS (pMOS) transistor 111, an n-channel MOS (nMOS) transistor 112, a resistor 151, a NAND gate 152, and an inverter 153.
The pMOS transistor 111 and the nMOS transistor 112 are connected in series between a high-potential power supply line VDD and a low-potential power supply line (ground line) VSS. Output control signals S11 and S12 are supplied to the gates of the transistors 111 and 112, respectively.
An input terminal 102 is connected to a connection node between the transistors 111 and 112, and is also connected to one of input terminals of the NAND gate 152 via the resistor 151. An input block control signal S13 is supplied to the other one of the input terminals of the NAND gate 152. A signal output from the NAND gate 152 is input into an LSI via the inverter 153.
In the input circuit 100 illustrated in FIG. 1, if the input terminal 102 is used as an original input terminal, both the transistors 111 and 112 are brought into an OFF state by setting the output control signal S11 to a high level “H” and the output control signal S12 to a low level “L”.
Subsequently, by setting the input block control signal S13 to “H”, a signal supplied to the input terminal 102 is input into the LSI, that is, is supplied to a predetermined internal circuit of the LSI, via the resistor 151, the NAND gate 152, and the inverter 153.
On the other hand, if the input terminal 102 is used as an output terminal, only one of the transistors 112 and 111 is brought into an ON state by setting both the output control signals S11 and S12 to “H” or “L”. As a result, an “L” or “H” signal is output to the input terminal 102.
That is, a signal having logic opposite to that of the output control signals S11 and S12 is output from the input terminal (output terminal) 102.
At that time, the input block control signal S13 supplied to the other one of the input terminals of the NAND gate 152 is set to “L” and a signal transmitted from the input terminal 102 is blocked by the NAND gate 152 so as not to be input into the LSI.
FIG. 2 is a diagram describing an exemplary operation of the input circuit illustrated in FIG. 1 when the input terminal 102 included in the input circuit 100 uses a pull-up resistor 103.
As illustrated in FIG. 2, if both the transistors 111 and 112 are brought into the OFF state by setting the output control signal S11 to “H” and the output control signal S12 to “L”, diodes parasitic to the transistors 111 and 112 function as if they were connected to each other.
A direction in which the diode parasitic to the transistor 111 is connected to a power supply voltage is opposite to a direction in which the diode parasitic to the transistor 112 is connected to a power supply voltage. For example, these parasitic diodes function so as to prevent the input terminal 102 from destroying a circuit with static noise (electrostatic discharging (ESD)).
FIG. 3 is a simulation waveform diagram illustrating an example of a terminal voltage in the input circuit illustrated in FIG. 2. Referring to FIG. 3, a curve L11 represents a voltage waveform of a high-potential power supply line VDD (a waveform obtained when the potential of the high-potential power supply line VDD is changed at 144 MHz in the range of 5 V±2 Vp-p), and a curve L12 represents the waveform of the input terminal 102.
For example, if the potential of the high-potential power supply line VDD for supplying 5 V is changed at 144 MHz by ±2 V as indicated by the curve L11 illustrated in FIG. 3, the waveform of the input terminal 102 becomes the curve L12 illustrated in FIG. 3 by the diodes parasitic to the transistors 111 and 112 illustrated in FIG. 2.
For example, high-frequency noise is strongly applied to the high-potential power supply line VDD because of a radio wave (electromagnetic wave) of 144 MHz, a forward current passes through the parasitic diode on the side of the high-potential power supply line VDD and the level “H” of the input terminal 102 is instantaneously reduced when the potential of the high-potential power supply line VDD decreases (see, a period P11 illustrated in FIG. 3).
Since a forward current does not pass through the parasitic diode when the potential of the high-potential power supply line VDD increases, the input terminal 102 receives a current only from the pull-up resistor 103. As a result, the next decrease in the potential of the high-potential power supply line VDD occurs before the potential of the input terminal 102 decreases to the same potential as that of the high-potential power supply line VDD and the level of the input terminal 102 is reduced by a forward current passing through the parasitic diode.
If the above-described operation is repeated, the level “H” of the input terminal 102 is reduced, as indicated by the curve L12 illustrated in FIG. 3 (see, a period P12 illustrated in FIG. 3).
If such a phenomenon becomes pronounced, a signal of the level “L” may be erroneously input into the LSI via the NAND gate 152 and the inverter 153 despite the fact that the input terminal (input signal) 102 is not brought into the level “L” and a malfunction may occur.
FIGS. 2 and 3 illustrate a case in which the input terminal 102 is connected to the pull-up resistor 103. However, in a case where the input terminal 102 is connected to a pull-down resistor, a similar problem occurs.
That is, if a pull-down resistor is used, the level “L” of the input terminal 102 is increased by a mechanism similar to that described in the above-described case (by a forward current that passes through the parasitic diode on the side of the low-potential ground line VSS in response to the change in the potential of the low-potential ground line VSS). As a result, the level “L” of the input terminal 102 may be misidentified as the level “H” of the input terminal 102 and a malfunction may occur.
Japanese Laid-open Patent Publication Nos. 2000-101409 and 2000-036561 disclose semiconductor integrated circuits including input circuits used for noise reduction.